1. Field of the Invention
The invention is directed to a semiconductor chip for optoelectronics, particularly a radiation-emitting semiconductor chip, comprising:
an active thin-film layer, particularly on the basis of In1-x-yAlxGayP (whereby 0≦x≦1, 0≦y≦1 and x+y≦1 apply), in which a photon-emitting zone is formed, and
a carrier substrate for the thin-film layer that is arranged at a side of the thin-film layer that faces away from the emission direction and that is connected to it.
It is also directed to a method for the simultaneously manufacture of a plurality of such semiconductor chips.
2. Description of the Related Art
The carrier substrate is part of the semiconductor chip in and of itself and mechanical support for the thin-film layer, which itself no longer comprises a self-supporting layer at that side lying opposite the carrier substrate.
Thin-film layer on the basis of In1-x-yAlxGayP (where 0≦x≦1, 0≦y≦1 and x+y≦1 apply) means that the thin-film layer comprises a plurality of layers that are manufactured of doped or undoped material from the system In1-x-yAlxGayP (where 0≦x≦1, 0≦y≦1 and x+y≦1).
Semiconductor chips of the species initially cited are disclosed by U.S. Pat. Nos. 5,008,718 and 5,367,580. For manufacturing a semiconductor chip of the known type, an active semiconductor layer sequence is usually applied on a substrate using an epitaxy process. Subsequently, a carrier substrate is secured on the upper side of the active semiconductor layer sequence. The substrate on which the semiconductor layer sequence had been deposited is at least partially removed.
A metallic reflection layer is advantageously situated between the carrier substrate and the active semiconductor layer sequence, so that no light is absorbed by the carrier substrate.
One disadvantage of the known semiconductor chip is that the metallic reflection layer arranged between carrier substrate and the active semiconductor layer sequence generally does not comprise a satisfactory reflectivity given short wavelengths. Gold becomes more and more inefficient as a metallic reflection layer, particularly at a wavelength of less than 600 nm, since the reflectivity significantly decreases. For example, the elements Al and Ag, whose reflectivity remains comparatively constant at wavelengths shorter than 600 nm, can be employed at wavelengths below 600 nm.
The bonding of large surfaces like the metallic reflection layer are currently problematic. The bonding and the alloying of the metallic contact layer also results in a considerable risk for a deterioration of the quality of the metallic reflection layer.
German patent document DE 198 07 758 A1 also discloses a semiconductor shaped like a truncated pyramid that comprises an active, light-emitting zone between an upper window layer and a lower window layer. Together, the upper window layer and the lower window layer form a base body having the shape of a truncated pyramid. The result of the slanting alignment of the sidewalls of the window layers is that the light emanating from the active zone is totally reflected at the lateral surfaces and impinges the base surface of the truncated pyramid base body serving as luminous surface at nearly a right angle. As a result, a part of the light emitted by the active zone emerges onto the surface within the exit cone of the semiconductor element.
The “exit cone” is defined as the cone that is formed by light rays whose angle of incidence onto the exit face is less than the critical angle for the total reflection and that are therefore not totally reflected but directly coupled out from the semiconductor material. The aperture angle of the exit cone, consequently, is twice as large as the limit angle of the total reflection. Those light rays that proceed outside of the exit cone, i.e., impinge the exit face at an angle larger than the limit angle of the total reflection, are totally reflected.
In order to achieve a significant increase in the light yield, this concept assumes a minimum thickness for the upper and lower window layer. Given the known truncated pyramid semiconductor element, the thickness of the upper and lower window layer amounts to at least 50.8 μm (0.002 inches). Such a layer thickness is still doable. When, however, the power of the known semiconductor chip is to be increased, then it is necessary that all dimensions be scaled. This results in layer thicknesses that can only be manufactured with high outlay in an epitaxial way. If it can be scaled at all, then this known semiconductor chip can only be scaled with great technical outlay.